1. Field of the Invention
The present invention relates generally to An SRAM based CAM (Content Addressable Memory) cell with PFET passgate SRAM cells which results in a smaller cell size because of a more balanced number of PFET devices and NFET devices.
2. Discussion of the Prior Art
CAM (Content Addressable Memory) is the main component of internet routers and switches. CAM can also be used in many other applications such as pattern recognition and cryptography. A full ternary CAM cell in general consists of two memory bits and the compare logic. The full ternary CAM cell allows full array search with per bit masking. The memory bits may be provided by DRAM cells or SRAM cells. DRAM based CAM is smaller, but requires the more complex DRAM process and the refresh operation to maintain the data. SRAM based CAM is larger, but the fabrication process is cheaper and the design is simpler. A typical SRAM based CAM cell consists of 16 devices, with 4 PFETs providing the SRAM cell pull ups, and with 12 NFETs for the SRAM cells and for the compare logic. The size is very large, about 4-5 times the size of a typical 6T SRAM cell. A typical 6T SRAM cell consists of 2 pull up PFETs, 2 pull down NFETs and 2 passgate NFETs.
FIG. 1A is a circuit schematic, with a truth table of operation, of a prior art full ternary CAM cell with NFET passgates which comprises 16 transistors, 4 PFETs and 12 NFETS.
FIG. 1B is a circuit layout of the prior art full ternary CAM cell of FIG. 1A and illustrates further details of the prior art design at the 0.13 um node of CMOS technology, which is shown for circuit area comparison purposes with the full ternary CAM cell with PFET passgates of the present invention.
The present invention provides a Content Addressable Memory (CAM) with PFET passgate SRAM cells which results in a smaller cell size because of a more balanced number of 8 PFET devices and 8 NFET devices. Moreover, the use of PFET passgates allows the size of the SRAM cell pulldown devices to be reduced to a minimum size. The PFET passgates also consume less power as PFET off currents are generally much smaller than NFET off currents. The ratio is about 1 to 20. The standby power is further reduced because the SRAM pull down NFETs are smaller with the PFET passgates. With PFET passgates, the SRAM read/write bit lines can also be biased to some voltage level between GND and VDD, instead of to VDD as in the prior art. For example, if the read/write bit lines are biased at one half VDD, the SRAM read/write power can be lowered by 3/4. Thus the standby power dissipation and the read/write power are both reduced.